Thin film transistor array panel

ABSTRACT

A thin film transistor array panel includes: first and second gate lines disposed on a substrate and separated from each other; a data line intersecting the first and second gate lines; first and second thin film transistors connected to the first gate line and the data line; a third thin film transistor connected to the second gate line and having a drain electrode; and a pixel electrode including a first subpixel electrode and a second subpixel electrode, wherein the first subpixel electrode is connected to the first and third thin film transistor, the second subpixel electrode is connected to the second thin film transistor and includes a projection overlapping the drain electrode, and the projection has a first pair of edge portions that meet a first edge of the drain electrode and are substantially parallel to each other.

This application is a continuation of U.S. application Ser. No.12/018,885, filed on Jan. 24, 2008, which claims priority to KoreanPatent Application No. 10-2007-0007306, filed on Jan. 24, 2007, and allthe benefits accruing therefrom under 35 U.S.C. §119, the contents ofwhich in its entirety are herein incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel, andparticularly to a thin firm transistor array panel for a liquid crystaldisplay.

(b) Description of Related Art

A liquid crystal display (LCD) is one of the most widely used flat paneldisplays. An LCD includes two panels provided with field-generatingelectrodes such as pixel electrodes and a common electrode, a liquidcrystal (LC) layer interposed therebetween, and at least one polarizerattached to the panel(s). The LCD displays images by applying voltagesto the field-generating electrodes to generate an electric field in theLC layer, which determines orientations of LC molecules in the LC layerto adjust polarization of incident light, thereby displaying images.

Among the LCDs, a vertical alignment (VA) mode LCD, which aligns LCmolecules such that the long axes of the LC molecules are perpendicularto the panels in absence of electric field, is spotlighted because ofits high contrast ratio and wide reference viewing angle.

The wide viewing angle of the VA mode LCD can be realized by cutouts inthe field-generating electrodes and protrusions on the field-generatingelectrodes. Since the cutouts and the protrusions can determine the tiltdirections of the LC molecules, the tilt directions can be distributedinto several directions by appropriately arranging the cutouts and theprotrusions such that the reference viewing angle is widened.

However, the VALCD has relatively poor lateral visibility compared withfront visibility. In order to improve the lateral visibility, it issuggested that a pixel is divided into two subpixels having differentvoltages.

One of the improvements suggests that a driving circuit generatesindividual data voltages for the two subpixels and supplies thegenerated voltages to the subpixels. However, the driving scheme iscomplicated. Another of the improvements suggests that the two subpixelsare once supplied with the same data voltage and the voltages of thesubpixels are differentiated later by using capacitors. However, thevoltages of the subpixels may not be expectedly controlled and may notbe uniform.

SUMMARY OF THE INVENTION

A thin film transistor array panel according to an embodiment of thepresent invention includes: a substrate; a first gate line disposed onthe substrate; a second gate line disposed on the substrate andseparated from the first gate line; a data line intersecting the firstand second gate lines; a first thin film transistor connected to thefirst gate line and the data line; a second thin film transistorconnected to the first gate line and the data line; a third thin filmtransistor connected to the second gate line and having a drainelectrode; and a pixel electrode including a first subpixel electrodeand a second subpixel electrode, wherein the first subpixel electrode isconnected to the first and third thin film transistor, the secondsubpixel electrode is connected to the second thin film transistor andincludes a projection overlapping the drain electrode, and theprojection has a first pair of edge portions that meet a first edge ofthe drain electrode and are substantially parallel to each other.

Edges of the projection and edges of the drain electrode may form twointersections.

Edges of the projection and edges of the drain electrode may form fourintersections.

The projection may further comprise a second pair of edge portions thatmeet a second edge of the drain electrode and are substantially parallelto each other, and a distance between the edge portions in the firstpair along a first direction may be substantially the same as a distancebetween the edge portions in the second pair along the first direction.

The first edge and the second edge of the drain electrode may include afirst pair of drain edge portions substantially parallel to each otherand a second pair of drain edge portions substantially parallel to eachother.

A distance between the edge portions in the first pair of drain edgeportions along a second direction substantially perpendicular to thefirst direction may be substantially the same as a distance between theedge portions in the second pair of drain edge portions along the seconddirection.

The edge portions and the drain edge portions may be equal to or longerthan twice an allowable alignment error range.

The projection may have a shape of a bar and passes through the drainelectrode.

The projection has a uniform width, and the drain electrode may alsohave a uniform width.

The projection may have a branch fully overlapping the drain electrode.The thin film transistor array panel may further include a storageelectrode overlapping the drain electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describingembodiments thereof in detail with reference to the accompanying drawingin which:

FIG. 1 is a layout view of an LCD according to an embodiment of thepresent invention;

FIG. 2 is a layout view of a TFT array panel of the LCD shown in FIG. 1;

FIG. 3 is an expanded view of a portion of the TFT array panel shown inFIG. 2;

FIG. 4 is a sectional view of the portion shown in FIG. 3 taken alongline IV-IV; FIG. 5 is a layout view of a common electrode panel of theLCD shown in FIG. 1;

FIG. 6 is a sectional view of the LCD shown in FIG. 1 taken along lineVI-VI;

FIG. 7 is a sectional view of the LCD shown in FIG. 1 taken along lineVII-VII;

FIG. 8 is an equivalent circuit diagram of the LCD shown in FIGS. 1-7;

FIGS. 9 and 10 are layout views of LCDs according to another embodimentof the present invention;

FIG. 11 is an expanded view of an up-down capacitor shown in FIG. 10;

FIG. 12 is a layout view of an up-down capacitor according to anotherembodiment of the present invention; and

FIG. 13 is a schematic layout view of an up-down capacitor according toanother embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein. Like numerals refer to like elementsthroughout.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present.

An LCD according to an embodiment of the present invention will bedescribed in detail with reference to FIG. 1 to FIG. 7.

FIG. 1 is a layout view of an LCD according to an embodiment of thepresent invention. FIG. 2 is a layout view of a TFT array panel of theLCD shown in FIG. 1, FIG. 3 is an expanded view of a portion of the TFTarray panel shown in FIG. 2, FIG. 4 is a sectional view of the portionshown in FIG. 3 taken along line IV-IV, and FIG. 5 is a layout view of acommon electrode panel of the LCD shown in FIG. 1. FIG. 6 is a sectionalview of the LCD shown in FIG. 1 taken along line VI-VI, and FIG. 7 is asectional view of the LCD shown in FIG. 1 taken along line VII-VII.

Referring to FIGS. 1-7, an LCD according to an embodiment of the presentinvention includes a TFT array panel 100, a common electrode panel 200,and a liquid crystal layer 3 interposed between the panels 100 and 200.

First, the TFT array panel 100 will be described with reference to FIGS.1-4, 6 and 7.

A plurality of gate conductors including a plurality of gate lines 121and a plurality of storage electrode lines 131 are formed on aninsulating substrate 110 such as transparent glass or plastic.

The gate lines 121 transmit gate signals and extend substantially in atransverse direction. Each of the gate lines 121 includes an end portion129 having a large area for contact with another layer or an externaldriving circuit. A gate driving circuit (not shown) for generating thegate signals may be mounted on a flexible printed circuit (FPC) film(not shown), which may be attached to the substrate 110, directlymounted on the substrate 110, or integrated onto the substrate 110. Thegate lines 121 may extend to be connected to a driving circuit that maybe integrated on the substrate 110.

The storage electrodes 131 are supplied with a predetermined voltagesuch as a common voltage and each of the storage electrode lines 131includes a plurality of sets 133 of storage electrodes and a pluralityof storage connections 135.

Each set 133 of the storage electrodes includes first, second, third,fourth, and fifth storage electrodes 133 a, 133 b, 133 c, 133 d, 133 e.The first and the second storage electrodes 133 a and 133 b extend in alongitudinal direction and are connected to the fifth storage electrode133 e at their lower ends. The first storage electrode 133 a includes aprojection having an oblique edge relative to the gate lines 121. A leftportion of the fifth storage electrode 133 is wide and has an obliqueedge. The third and the four storage electrodes 133 c and 133 dobliquely extend approximately from a center of the first storageelectrode 133 a approximately to upper and lower ends of the secondstorage electrode 133 b, respectively.

Each of the storage connections 135 is connected to a first storageelectrode 133 a of a set 133 of storage electrodes and a second storageelectrode 133 b of another set 133 of storage electrodes adjacentthereto. However, the storage electrode lines 131 may have variousshapes and arrangements.

The gate conductors 121 and 131 may be made of Al containing metal suchas Al and Al alloy, Ag containing metal such as Ag and Ag alloy, Cucontaining metal such as Cu and Cu alloy, Mo containing metal such as Moand Mo alloy, Cr, Ta, or Ti. However, they may have a multi-layeredstructure including two conductive films (not shown) having differentphysical characteristics. One of the two films may be made of lowresistivity metal including Al containing metal, Ag containing metal,and Cu containing metal for reducing signal delay or voltage drop. Theother film may be made of material such as Mo containing metal, Cr, Ta,or Ti, which has good physical, chemical, and electrical contactcharacteristics with other materials such as indium tin oxide (ITO) orindium zinc oxide (IZO). Good examples of the combination of the twofilms are a lower Cr film and an upper Al (alloy) film and a lower Al(alloy) film and an upper Mo (alloy) film. However, the gate conductors121 and 131 may be made of various metals or conductors.

The lateral sides of the gate conductors 121 and 131 are inclinedrelative to a surface of the substrate 110, and the inclination anglethereof ranges about 30-80 degrees.

A gate insulating layer 140 that may be made of silicon nitride (SiNx)or silicon oxide (SiOx) is formed on the gate conductors 121 and 131.

A plurality of pairs of semiconductor islands 154 ab and 154 c that maybe made of hydrogenated amorphous silicon (abbreviated to “a-Si”) orpolysilicon are formed on the gate insulating layer 140. Each of thesemiconductor islands 154 ab is disposed on the gate lines 121.

Three ohmic contact islands 163 ab, 165 a and 165 b are formed on eachof the semiconductor islands 154 ab, and a pair of ohmic contact islands163 c and 165 c are formed on each of the semiconductor islands 154 c.The ohmic contacts 163 ab, 163 c, 165 a, 165 b and 165 c may be made ofn+ hydrogenated a-Si heavily doped with n type impurity such asphosphorous or they may be made of silicide.

The lateral sides of the semiconductor islands 154 ab and 154 c and theohmic contacts 163 ab, 163 c, 165 a, 165 b and 165 c are inclinedrelative to the surface of the substrate 110, and the inclination anglesthereof may be in a range of about 30-80 degrees.

A plurality of data conductors including a plurality of data lines 171,a plurality of source electrodes 173 c, and a plurality of drainelectrodes 175 a, 175 b and 175 c are formed on the ohmic contacts 163ab, 163 c, 165 a, 165 b and 165 c and the gate insulating layer 140.

The data lines 171 transmit data signals and extend substantially in thelongitudinal direction to intersect the gate lines 121 and the storageconnections 135. Each of the data lines 171 includes an end portion 179having a large area for contact with another layer or an externaldriving circuit. A data driving circuit (not shown) for generating thedata signals may be mounted on a FPC film (not shown), which may beattached to the substrate 110, directly mounted on the substrate 110, orintegrated onto the substrate 110. The data lines 171 may extend to beconnected to a driving circuit that may be integrated on the substrate110.

Each of the data lines 171 includes a plurality of source electrodeportions 173 ab projecting left toward the gate lines 121 andoverlapping the semiconductor islands 154 ab. Each of the portions 173ab has two concavities that form first and second source electrodes.

The source electrodes 173 c, namely, the third source electrodes 173 care separated from the data lines 171. Each of the third sourceelectrodes 173 c extends upward from an end portion overlapping thesemiconductor island 154 c, detours around the source electrode portion173 ab, overlaps the second storage electrodes 133 b, and extendparallel to the data line 171. The other end portion of the third sourceelectrode 173 somewhat expands for contact with other layers.

The first to third drain electrodes 175 a, 175 b and 175 c are separatedfrom one another and from the data lines 171 and the third sourceelectrodes 173 c.

The first and the second drain electrodes 175 a and 175 b extenddownward from one end portions overlapping the semiconductor island 154ab and the other end portions of the first and the second drainelectrodes 175 a and 175 b have width wider than other portions. Thefirst drain electrode 175 a overlaps the second storage electrode 133 band one end portion of the first drain electrode 175 a faces the firstsource electrode. One end portion of the second drain electrode 175 cfaces the second source electrode.

The third drain electrode 175 c has a shape of a bar having a uniformwidth and extends in the longitudinal direction. One end portion of thethird drain electrode 175 c overlaps the semiconductor island 154 c andfaces the third source electrodes 173 c, and the other end portion ofthe third drain electrode 175 c overlaps the fifth storage electrode 133e.

A portion of the gate line 121 overlapping the first source electrodeand the first drain electrode 175 a is to be a first gate electrode 124a, and another portion of the gate line 121 overlapping the secondsource electrode and the second drain electrode 175 b is to be a secondgate electrode 124 b. In addition, a portion of the gate line 121overlapping the third source electrode 173 c and the third drainelectrode 175 c is to be a third gate electrode 124 c. The first tothird gate electrodes 124 a, 124 b, 124 c may project upward ordownward.

A first gate electrode 124 a, a first source electrode, and a firstdrain electrode 175 a along with a semiconductor island 154 ab form aTFT having a channel formed in a portion of the semiconductor island 154ab disposed between the first source electrode and the first drainelectrode 175 a. A second gate electrode 124 b, a second sourceelectrode, and a second drain electrode 175 c along with a semiconductorisland 154 ab form a TFT having a channel formed in a portion of thesemiconductor island 154 ab disposed between the second source electrodeand the second drain electrode 175 b. In addition, a third gateelectrode 124 c, a third source electrode 173 c, and a third drainelectrode 175 along with a semiconductor island 154 c form a TFT havinga channel formed in a portion of the semiconductor island 154 c disposedbetween the third source electrode 173 c and the third drain electrode175 c.

The data conductors 171, 173 c, 175 a, 175 b, 175 c may be made ofrefractory metal such as Cr, Mo, Ta, Ti, or alloys thereof. However,they may have a multilayered structure including a refractory metal film(not shown) and a low resistivity film (not shown). Good examples of themulti-layered structure are a double-layered structure including a lowerCr/ Mo (alloy) film and an upper Al (alloy) film and a triple-layeredstructure of a lower Mo (alloy) film, an intermediate Al (alloy) film,and an upper Mo (alloy) film. However, the data conductors 171, 173 c,175 a, 175 b, 175 c may be made of various metals or conductors.

The data conductors 171, 173 c, 175 a, 175 b, 175 c have inclined edgeprofiles, and the inclination angles thereof range about 30-80 degrees.

The ohmic contacts 163 ab, 163 c, 165 a, 165 b and 165 c are interposedonly between the underlying semiconductor islands 154 ab and 154 c andthe overlying data conductors 171, 173 c, 175 a, 175 b, 175 c thereonand reduce the contact resistance therebetween. The semiconductorislands 154 ab and 154 c include some exposed portions, which are notcovered with the data conductors 171, 173 c, 175 a, 175 b, 175 c, suchas portions located between the first to third source electrodes 173 aband 173 c and the first to third drain electrodes 175 a-175 c.

A passivation layer 180 is formed on the data conductors 171, 173 c, 175a, 175 b, 175 c and the exposed portions of the semiconductor islands154 ab and 154 c. The passivation layer 180 may be made of an inorganicinsulator or an organic insulator and it may have a flat top surface.Examples of the inorganic insulator include silicon nitride and siliconoxide. The organic insulator may have photosensitivity and dielectricconstant less than about 4.0. The passivation layer 180 may include alower film of an inorganic insulator and an upper film of an organicinsulator such that it takes the excellent insulating characteristics ofthe organic insulator while preventing the exposed portions of thesemiconductor islands 154 ab and 154 c from being damaged by the organicinsulator.

The passivation layer 180 has a plurality of contact holes 182 exposingthe end portions 179 of the data lines 171, a plurality of contact holes183 c exposing the wide end portions of the third source electrode 173c, and a plurality of contact holes 185 a and 185 b exposing the wideend portions of the first and the second drain electrodes 175 a and 175b, respectively. The passivation layer 180 and the gate insulating layer140 have a plurality of contact holes 181 exposing the end portions 129of the gate lines 121.

A plurality of pixel electrodes 191 and a plurality of contactassistants 81 and 82 are formed on the passivation layer 180. They maybe made of transparent conductor such as ITO or IZO or reflectiveconductor such as Ag, Al, Cr, or alloys thereof.

The contact assistants 81 and 82 are connected to the end portions 129of the gate lines 121 and the end portions 179 of the data lines 171through the contact holes 181 and 182, respectively. The contactassistants 81 and 82 protect the end portions 129 and 179 and enhancethe adhesion between the end portions 129 and 179 and external devices.

Each of the pixel electrodes 191 is approximately a rectangle that hasfour main edges nearly parallel to the gate lines 121 or the data lines171 as well as chamfered upper and lower left corners. The chamferededges of the pixel electrode 191 make an angle of about 45 degrees withthe gate lines 121. A left edge of the pixel electrode 191 is disposedon the first storage electrode 133 a and a portion of a right edge ofthe pixel electrode 191 is disposed on the second storage electrode 133b. The oblique edge of the first storage electrodes 133 a may beparallel to a chamfered edge of the pixel electrode 191 adjacentthereto.

The pixel electrode 191 includes a first subpixel electrode 191 a and asecond subpixel electrode 191 b divided by a gap 92, and itsubstantially has an inversion symmetry with respect to an imaginarytransverse line bisecting the pixel electrode 191.

The gap 92 includes an upper portion 92 a, a lower portion 92 b, and alongitudinal portion 92 c. The upper and lower portions 92 a and 92 bobliquely extend approximately from the left edge of the pixel electrode191 approximately to the right edge of the pixel electrode 191 andoverlap the third and fourth storage electrodes 133 c and 133 d,respectively. The upper and lower portions 92 a and 92 b of the gap 92make an angle of about 45 degrees with the gate lines 121 and they makea right angle with each other.

The first subpixel electrode 191 a is an isosceles trapezoid rotated bya right angle according to the shape of the gap 92. The right edge ofthe first subpixel electrode 191 a overlaps the second storage electrode133 b, and the first subpixel electrode 191 a has a cutout 91 extendingfrom around a center of the right edge along the imaginary transverseline. An inlet of the cutout 91 is formed by a pair of inclined edgessubstantially parallel to the lower cutout 92 a and the upper cutout 92b, respectively. The gap 92 is also named as a cutout for descriptiveconvenience.

The first subpixel electrode 191 a is connected to the first drainelectrode 175 a and the third source electrode 173 c through the contactholes 185 a and 183 c.

The second subpixel electrode 191 b includes an upper electrode portion191 b 1, a lower electrode portion 191 b 2, a connecting portion 191 b3, and a projection 195.

The upper and lower electrode portions 191 b 1 and 191 b 2 are nearlyright-angled trapezoids rotated by a right angle, when the chamferedcorners are not considered. The right edges of the upper and lowerelectrode portions 191 b 1 and 191 b 2 are spaced apart from the firstdrain electrode 175 a and the third source electrode 173 c so that theupper and lower electrode portions 191 b 1 and 191 b 2 do not overlapare the first drain electrode 175 a and the third source electrode 173c, and thus the upper and lower electrode portions 191 b 1 and 191 b 2are disposed left to the right edge of the first subpixel electrode 191a. The upper electrode portion 191 b 1 is connected to the second drainelectrode through the contact hole 185 b. The connecting portion 191 b 3connects the upper electrode portion 191 b 1 and the lower electrodeportion 191 b 2, and it overlaps the first storage electrode 133 a suchthat its left edge is disposed on the first storage electrode 133 a andits right edge is disposed outside the first storage electrode 133 a.

Most of the projection 195 is disposed on the fifth storage electrode133 e and has a shape of a bar. The projection 195 extends downward fromthe meeting point of the lower left oblique edge and the left edge ofthe lower electrode portion 191 b 2, turns right, and overlaps andpasses through the third drain electrode 175 c. As shown in FIGS. 3 and4, a portion of the projection 195 disposed near the intersection withthe third drain electrode 175 c has a uniform width, and so the thirddrain electrode 175 c does. The bar-shaped projection 195 and the thirddrain electrode 175 c pass through each other. In detail, the right endof the projection 195 is located outside the third drain electrode 175c, and similarly, the upper end of the third drain electrode 175 c islocated outside the projection 195. This configuration is establishedby, when the LCD is designed, making the distance d1 between the rightend of the projection 195 and the right edge of the third drainelectrode 175 c larger than the allowable misalignment error D1 in thetransverse direction in the fabrication of thin film patterns and thedistance d2 between the upper edge of the projection 195 and the upperend of the third drain electrode 175 c larger than the allowablemisalignment error D2 in the longitudinal direction in the fabricationof thin film patterns. This configuration makes the overlapping areauniform regardless of the misalignment within the allowable misalignmenterror D1 and D2.

For example, although the projection 195 is formed in a position locatedaside from the correct position left and up by an amount of allowablemisalignment error D1 and D2 as shown in FIGS. 3 and 4, the overlappingarea CA2 between the projection 195 and the third drain electrode 175 cis substantially the same as the overlapping area CA1 for the correctposition. This is also true when the projection 195 and the third drainelectrode 175 c are misaligned in any direction.

The description of the common electrode panel 200 follows with referenceto FIGS. 1, 5 and 7.

A light blocking member 220 referred to as a black matrix for preventinglight leakage is formed on an insulating substrate 210 such astransparent glass or plastic. The light blocking member 220 has aplurality of openings 225 facing the pixel electrodes 191 and theopenings 225 may have substantially the same planar shape as the pixelelectrodes 191. Otherwise, the light blocking member 220 may include aplurality of rectilinear portions facing the data lines 171 on the TFTarray panel 100 and a plurality of widened portions facing the TFTs onthe TFT array panel 100.

A plurality of color filters 230 are also formed on the substrate 210and they are disposed substantially in the areas enclosed by the lightblocking member 220. The color filters 230 may extend substantially inthe longitudinal direction along the pixel electrodes 191. Each of thecolor filters 230 may represent one of the primary colors such as red,green and blue colors.

An overcoat 250 is formed on the color filters 230 and the lightblocking member 220. The overcoat 250 may be made of (organic) insulatorand it prevents the color filters 230 from being exposed and provides aflat surface. The overcoat 250 may be omitted.

A common electrode 270 is formed on the overcoat 250. The commonelectrode 270 may be supplied with the common voltage and made oftransparent conductive material such as ITO and IZO.

The common electrode 270 has a plurality of sets 70 of cutouts. A set 70of cutouts 71-72 b faces a pixel electrode 191 and include a centercutout 71, a lower cutout 72 a, and an upper cutout 72 b. Each of thecutouts 71-72 b is disposed between adjacent cutouts 91-92 b of thepixel electrode 191 or between a cutout 92 a or 92 b and a chamferededge of the pixel electrode 191. Each of the cutouts 71-72 b has atleast an oblique portion having a depressed notch and extendingsubstantially parallel to the lower cutout 92 a or the upper cutout 92 bof the pixel electrode 191. The cutouts 71-72 b have substantially aninversion symmetry with respect to the above-described imaginarytransverse line bisecting the pixel electrode 191.

Each of the lower and upper cutouts 72 a and 72 b includes an obliqueportion, a transverse portion, and a longitudinal portion. The obliqueportion extends approximately from a left edge of the pixel electrode191 approximately to lower or upper edge of the pixel electrode 191.Each of the transverse and the longitudinal portions extends from arespective end of the oblique portion along an edge of the pixelelectrode 191, overlapping the edge of the pixel electrode 191, andmaking an obtuse angle with the oblique portion.

The center cutout 71 includes a central transverse portion, a pair ofoblique portions, and a pair of terminal longitudinal portions. Thecentral transverse portion extends approximately from the left edge ofthe pixel electrode 191 along the above-described transverse line. Theoblique portions extend from an end of the central transverse portionapproximately to the right edge of the pixel electrode 191 and makeoblique angles with the central transverse portion. The terminallongitudinal portions extend from the ends of the respective obliqueportions along the right edge of the pixel electrode 191, overlappingthe right edge of the pixel electrode 191, and making obtuse angles withthe respective oblique portions.

The pixel electrode 191 may have further cutouts substantially parallelto the upper portion 92 a and the lower portion 92 b of the gap 92, andaccordingly, the common electrode 270 may also have further cutouts. Thenumber of the cutouts 71-72 b, 91 and 92 may be varied depending on thedesign factors such as the size of the pixel electrode 190, the ratio ofthe transverse edges and the longitudinal edges of the pixel electrode190, the type and characteristics of the liquid crystal layer 3, and soon. The light blocking member 220 may also overlap the cutouts 71-72 bto block the light leakage through the cutouts 71-72 b.

Alignment layers 11 and 21 that may be homeotropic are coated on innersurfaces of the panels 100 and 200, and polarizers 12 and 22 areprovided on outer surfaces of the panels 100 and 200 so that theirpolarization axes may be crossed and one of the polarization axes may beparallel to the gate lines 121. One of the polarizers 12 and 22 may beomitted when the LCD is a reflective LCD.

The LCD may further include at least one retardation film (not shown)for compensating the retardation of the LC layer 3. The LCD may furtherinclude a backlight unit (not shown) supplying light to the LC layer 3through the polarizers 12 and 22, the retardation film, and the panels100 and 200.

It is preferable that the LC layer 3 has negative dielectric anisotropyand it is subjected to a vertical alignment that the LC molecules 31 inthe LC layer 3 are aligned such that their long axes are substantiallyvertical to the surfaces of the panels 100 and 200 in absence ofelectric field. Accordingly, incident light cannot pass the crossedpolarization system 12 and 22.

The above-described LCD is represented by an equivalent circuit shown inFIG. 8.

Referring to FIG. 8, a pixel of the LCD includes a first subpixel PX1, asecond subpixel PX2, and a voltage control element VC. The firstsubpixel PX1 includes a first TFT Q1, and a first liquid crystalcapacitor Clca and a first storage capacitor Csta connected to the firstTFT Q1, and the second subpixel PX2 includes a second TFT Q2, and asecond liquid crystal capacitor Clcb and the second storage capacitorCstb connected to the second TFT Q2. The voltage control element VCincludes a third TFT Q3, and an up-down capacitor CU and a third storagecapacitor Cstc.

The first liquid crystal capacitor Clca includes the first subpixelelectrode 191 a as one terminal, a corresponding portion of the commonelectrode 270 as the other terminal, and a portion of the liquid crystallayer 3 disposed between the two terminals as a dielectric. Similarly,the second liquid crystal capacitor Clcb includes the second subpixelelectrode 191 b as one terminal, a corresponding portion of the commonelectrode 270 as the other terminal, and a portion of the liquid crystallayer 3 disposed between the two terminals as a dielectric.

The first and second storage capacitor Csta and Cstb include the firstsubpixel electrode 191 a and the second subpixel electrode 191 b as oneterminals, respectively, the storage electrode line 131 as the otherterminals, and portions of the gate insulating layer 140 and thepassivation layer 180 disposed between the two terminals as adielectric.

The up-down capacitor CU is formed by the projection 195 of the secondsubpixel electrode 191 b, the drain electrode 175 c of the third TFT Q3,and a portion of the passivation layer 180 disposed therebetween.

The third storage capacitor Cstc includes two components, one beingformed by the drain electrode 175 c of the third TFT Q3, the commonelectrode 270, and the liquid crystal layer 3 disposed therebetween, andthe other being formed by the drain electrode 175 c of the third TFT Q3,the storage electrode line 131, and the gate insulating layer 140disposed therebetween.

The first to third storage capacitors Csta, Cstb and Cstc compensate forthe capacitances of the first liquid crystal capacitor Clca, the secondliquid crystal capacitor Clcb, and the up-down capacitor CU,respectively.

It is noted that the first and second TFTs Q1 and Q2 are connected tothe same gate line 121 n while the third TFT Q3 is connected to anthergate line 121 p, i.e., the post gate line 121 p.

Now, the operation of the LCD will be described in detail.

When a gate-on voltage is applied to the gate line 121 n, the first andsecond TFTs Q1 and Q2 turn on and thus a data voltage in the data line171 is applied to both the first subpixel electrode 191 a and the secondsubpixel electrode 191 b, simultaneously. Therefore, the first liquidcrystal capacitor Clca and the second liquid crystal capacitor Clcb arecharged with the same voltage.

When the next gate line 121 p is supplied with the gate-on voltage afterthe first and second TFTs Q1 and Q2 turn off, the third TFT Q3 turns on.Then, the first subpixel electrode 191 a and the drain electrode 175 cof the third TFT Q3 are electrically connected to each other, and theelectric charges stored in the first subpixel electrode 191 a and in thedrain electrode 175 c of the third TFT Q3 are redistributed to vary thevoltages of the first subpixel electrode 191 a and the third drainelectrode 175 c. At this time, the voltages of the first subpixelelectrode 191 a and the third drain electrode 175 c vary in oppositedirections. That is, if the voltage of the first subpixel electrode 191a decreases, the voltage of the third drain electrode 175 c increases.On the contrary, the voltage of the first subpixel electrode 191 a riseswhile the voltage of the third drain electrode 175 c falls down.

During the variation of the third drain electrode 175 c, the secondsubpixel electrode 191 b, forming two terminals of the up-down capacitorCU along with the third drain electrode 175 c, is floating, and thus thevoltage of the second subpixel electrode 191 b varies in the samedirection as that of the third drain electrode 175 c according to thevariation of the third drain electrode 175 c. Therefore, the shiftdirection of the second subpixel electrode 191 b is opposite that of thefirst subpixel electrode 191 a, thereby the voltages of the first liquidcrystal capacitor Clca and the second liquid crystal capacitor Clcb aredifferentiated.

The amount of the voltage variation of the first and second subpixelelectrodes 191 a and 191 b depends on the capacitance of the up-downcapacitor CU. When the capacitance of the up-down capacitor CU isdifferent pixel by pixel, the voltage of the first subpixel electrode191 a and the third drain electrode 175 c is different pixel by pixelafter the first subpixel electrode 191 a and the third drain electrode175 c are connected to each other under the application of the same datavoltage. Hence, the capacitances of the up-down capacitors CU areuniform all over the pixels in order to obtain the same voltage when thesame data voltage is applied to the pixels. In other words, theoverlapping areas CA1 and CA2 of the projection 195 and the third drainelectrode 175 c forming the up-down capacitor CU are uniform regardlessof the misalignment as described above with reference to FIGS. 3 and 4.

When the potential difference is generated across the first LC capacitorClca or the second LC capacitor Clcb, an electric field substantiallyperpendicular to the surfaces of the panels 100 and 200 is generated inthe LC layer 3 and both the pixel electrode 190 and the common electrode270 are commonly referred to as field generating electrodes hereinafter.Then, the LC molecules in the LC layer 3 tilt in response to theelectric field such that their long axes are perpendicular to the fielddirection. The degree of the tilt of the LC molecules determines thevariation of the polarization of light incident on the LC layer 3 andthe variation of the light polarization is transformed into thevariation of the light transmittance by the polarizers 12 and 22. Inthis way, the LCD displays images.

The tilt angle of the LC molecules depends on the strength of theelectric field. Since the voltage of the first LC capacitor Clca and thevoltage of the second LC capacitor Clcb are different from each other,the tilt direction of the LC molecules in the first subpixel PX1 isdifferent from that in the second subpixel PX2 and thus the luminance ofthe two subpixels is different. Accordingly, with maintaining theaverage luminance of the two subpixels PX1 and PX2 in a targetluminance, the voltages of the first and second subpixels PX1 and PX2can be adjusted so that an image viewed from a lateral side is theclosest to an image viewed from the front, thereby improving the lateralvisibility.

Since the voltages of the first and second liquid crystal capacitorsClca and Clcb determine the luminance of the pixel, the luminance of thetwo subpixels PX1 and PX2 is different between pixels and furthermore,the average luminance of the two subpixels PX1 and PX2 may be differentbetween pixels so that the uniformity of the image display is degradedif the voltages of the first and second subpixel electrodes 191 a and191 b are different between pixels when applying the same data voltage.In this reason, it is significant that the capacitance of the up-downcapacitor CU is uniform.

Next, LCDs according to other embodiments of the present invention willbe described in detail with reference to FIG. 9 to FIG. 12.

FIGS. 9 and 10 are layout views of LCDs according to other embodimentsof the present invention, FIG. 11 is an expanded view of a up-downcapacitor shown in FIG. 10, and FIG. 12 is a layout view of an up-downcapacitor according to another embodiment of the present invention.

The LCDs according to these embodiments have structures similar to thatshown in FIGS. 1-7, except for the shapes of projections 196, 197 and198 and third drain electrodes 175 c.

Each of the projections 196, 197 and 198 shown in FIGS. 9-12 extendsdownward from the meeting point of the lower left oblique edge and thelower edge of the lower electrode portion 191 b 2, turns left, andoverlaps the third drain electrode 175 c.

Referring to FIG. 9, the projection 196 and the third drain electrode175 c have shapes of bar near an overlapping area CB like those shown inFIGS. 1-7.

Referring to FIGS. 10 and 11, a portion of the third drain electrode 175c disposed near an overlapping area CC is nearly a combination of arectangle and a triangle attached to the upper edge of the rectangle.The projection 197 has a bar shape near the overlapping area CC andpasses through the third drain electrode 175 c.

The projection 197 includes a rectangular branch disposed near the leftedge of the third drain electrode 175 c and extending upward. Therectangular branch is disposed within the overlapping area CC.Considering the misalignment margin, the distance d31 from the left edgeof the third drain electrode 175 c to the left edge of the rectangularbranch and the distance d32 from the left edge of the third drainelectrode 175 c to the left end of the projection 197 are designed to belarger than the allowable transverse alignment error range. In addition,it is designed such that the upper edge of the rectangular branch doesnot meet the upper edge of the third drain electrode 175 c under theconsideration of the misalignment. For example, it is designed so thatthe distance d5 between the upper edge of the rectangular portion of thethird drain electrode 175 c and the upper edge of the rectangular branchis greater than the allowable misalignment margin as shown in FIG. 11.

The projection 197 is curved at the right side of the overlapping areaCC toward the lower electrode portion 191 b 2, and thus it is designedsuch that the distance d4 between the curve position and the third drainelectrode 175 c is larger than the allowable misalignment margin.Furthermore, the distance d6 between the lower edge of the projection197 and the lower edge of the rectangular portion of the third drainelectrode 175 c is designed to be greater than the allowablemisalignment margin.

The third drain electrode 175 c shown in FIG. 12 becomes is nearly arectangle near the overlapping area CC, and the projection 198 is a barshape near the overlapping area CC. However, the projection 198 does notpass through the third drain electrode 175 c unlike previousembodiments. In this case, the overlapping area CD varies upon thetransverse misalignment while the longitudinal misalignment does notchange the overlapping area CD.

The condition for obtaining uniform overlapping area regardless of themisalignment is further generalized, which is described with referenceto FIG. 13.

FIG. 13 schematically shows overlapping of two members.

Referring to FIG. 13, the first member 1 passes through the secondmember 2 and the number of intersections of the edges of the firstmember 1 and the second member 2 is four. The left edge of the secondmember 2 meets edges of the first member 1 twice, and the right edge ofthe second member 2 also meets the edges of the first member 1 twice.

The first member 1 has four edge portions near the intersections, andeach of the four edge portions having a length substantially equal to orgreater than twice the allowable alignment error margin D. A pair ofedge portions that meet the left edge of the second member 2 aresubstantially parallel to each other, and another pair of edge portionsthat meet the right edge of the second member 2 are substantiallyparallel to each other and may not be parallel to the former pair ofedge portions. The longitudinal distance L between the two edge portionsin one pair is substantially the same as the longitudinal distance Lbetween the two edge portions in the other pair.

Furthermore, although remaining edge portions disposed between theparallel edge portions can have any shape, they are disposed within thesecond member 2 and thus they are designed to be spaced apart from theedges of the second member 2 by a distance greater than the allowablealignment error range D.

This configuration gives uniform overlapping area regardless oftransverse misalignment that lies within the allowable alignment errorrange D.

Similarly, when the edges of the second member 2 meet theabove-described condition, the overlapping area maintains uniformregardless of longitudinal misalignment.

It is noted that the projection 198 shown in FIG. 12 has only one pairof parallel edges portions.

Although preferred embodiments of the present invention have beendescribed in detail hereinabove, it should be clearly understood thatmany variations and/or modifications of the basic inventive conceptsherein taught which may appear to those skilled in the present art willstill fall within the spirit and scope of the present invention, asdefined in the appended claims.

1. A thin film transistor array panel comprising: a substrate; a firstgate line disposed on the substrate; a second gate line disposed on thesubstrate and separated from the first gate line; a data lineintersecting the first and second gate lines; a first thin filmtransistor connected to the first gate line and the data line; a secondthin film transistor connected to the first gate line and the data line;a third thin film transistor connected to the second gate line andhaving a drain electrode; and a pixel electrode including a firstsubpixel electrode and a second subpixel electrode, wherein the firstsubpixel electrode is connected to the first and third thin filmtransistor, the second subpixel electrode is connected to the secondthin film transistor and includes a projection overlapping the drainelectrode, and the projection has a first pair of edge portions thatmeet a first edge of the drain electrode and are substantially parallelto each other.
 2. The thin film transistor array panel of claim 1,wherein edges of the projection and edges of the drain electrode formtwo intersections.
 3. The thin film transistor array panel of claim 1,wherein edges of the projection and edges of the drain electrode formfour intersections.
 4. The thin film transistor array panel of claim 3,wherein the projection further comprises a second pair of edge portionsthat meet a second edge of the drain electrode and are substantiallyparallel to each other, and a distance between the edge portions in thefirst pair along a first direction is substantially the same as adistance between the edge portions in the second pair along the firstdirection.
 5. The thin film transistor array panel of claim 4, whereinthe first edge and the second edge of the drain electrode comprises afirst pair of drain edge portions substantially parallel to each otherand a second pair of drain edge portions substantially parallel to eachother.
 6. The thin film transistor array panel of claim 5, wherein adistance between the edge portions in the first pair of drain edgeportions along a second direction substantially perpendicular to thefirst direction is substantially the same as a distance between the edgeportions in the second pair of drain edge portions along the seconddirection.
 7. The thin film transistor array panel of claim 6, whereinthe edge portions and the drain edge portions are equal to or longerthan twice an allowable alignment error range.
 8. The thin filmtransistor array panel of claim 6, wherein the projection has a shape ofa bar and passes through the drain electrode.
 9. The thin filmtransistor array panel of claim 8, wherein the projection has a uniformwidth.
 10. The thin film transistor array panel of claim 9, wherein thedrain electrode has a uniform width.
 11. The thin film transistor arraypanel of claim 6, wherein the projection has a branch fully overlappingthe drain electrode.
 12. The thin film transistor array panel of claim1, further comprising a storage electrode overlapping the drainelectrode.